|
Six more weeks of winter was predicted by famous groundhog Punxsutawney Phil. The pudgy prognosticator also discussed his den’s new data acquisition technology.
“I was ground down looking for my shadow,”
explained Phil in a statement. “So I built an isolated, low-jitter sensor system using NVE parts. It eliminated ground loops even though I live in a ground loop.” |
|
|
|
“Ground loops, when they begin to take root, are plants of rapid growth.”
—George Washington
“Put your isolators in the right place, then stand firm.”
—Abraham Lincoln
“Defense of isolation is no vice.”
—George H. W. Bush
“NVE
has great sensorization and isolatorism.”
—George W. Bush |
|
|
|
“It’s a Magnet” and “Electricity” are on NVE’s background music playlist.
The theme is because NVE’s use of spintronics is a unique combination of magnetics and electronics, providing unprecedented miniaturization, precision, speed, and ruggedness.
<Lyrics> |
|
|
|
|
|
 |
|
Love Spintronics |
|
|
With Valentine’s Day coming up, we at NVE want to explain why we love spintronics.
We pioneered spintronics, which utilizes electron spin rather than electron charge for better sensors and isolators. Most of our products are based on spintronic giant magnetoresistance (“GMR”).
“Giant” refers to a giant change in resistance. The magic of GMR is turning the esoteric property of electron spin into resistance, which can be used by conventional electronics. The large signals can mean smaller size, more precision, and lower power.
Three products that use GMR:
• magnetic sensors
• gear-tooth sensors; and
• isolators.
We summarize spintronics advantages with four “Bs”:
• Boxes—Miniaturization and smaller packages
• Bits—3x more precise than competing semiconductors
• Bulletproof—virtually indestructible; unlimited life
• Batteries—Power as low as nanowatts
Check out our GMR overview video:
So this Valentine’s Day, fall in love with spintronics.
<More on GMR and Spintronics>
|
|
|
|
Upcoming Exhibitions |
|
|
IsoLoop distributor HY LINE Power Components is exhibiting at the Embedded World exhibition, February 28 to March 1 in Nuremberg, Germany. IsoLoop Isolated Bus Transceivers are popular for embedded applications.
|
|
|
Application Corner |
|
|
Package Dimension FAQs
Q. What are the package tolerances of NVE parts?
A. NVE takes great care to ensure its parts will work in any board layout within reason (and some not within reason).
All of our parts fully conform to applicable JEDEC standards, plus they meet rigorous standards for pin planarity, pitch, and offset to ensure every pin solders correctly.
Q. What are “BASIC dimensions”?
All NVE parts meet or exceed applicable JEDEC standards. The package below fully complies with JEDEC MS-012, for example:
SOIC-8 Package Side View
NVE datasheets generally use geometric tolerancing standards. As noted in the drawing, pin spacing is a BASIC
dimension, meaning the tolerance do not accumulate. In this case, the pin placement tolerance for each pin is ±0.01 inch from the ideal position.
Even though there are three spaces between the first and last pins, the tolerance of the last pin is still ±0.01 inch from the ideal position.
Q. What are planarity, pitch, and offset, and why are they important?
Planarity specifies the up or down position of the pins. It's important because an out-of-plane pin might not be close enough to the solder pad to make contact as the solder reflows. This can be difficult to detect on a printed-circuit assembly.
Pitch specifies the distance between pins. This is important to ensure the pins contact the solder pad but not an adjacent pad.
Offset is a measure of the distance of the pin from the package. It is important to ensure the pins will contact the solder pad and not nearby traces or pads.
NVE uses precision leadframes and has quality systems in place to ensure customers never see a bent pin. Parts are double inspected for planarity, pitch, and offset.
Q. What is the recommended solder-pad layout?
NVE takes care to ensure its parts will work in your board layout. The following diagram shows a typical SOIC-8 pad layout, and standard library layouts are fine:
SOIC-8 Solder-Pad Layout |
|
